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AC'97 2.1 FEATURES Variable Sample Rate Audio AC'97 FEATURES AC'97 2.2 Compliant Greater than 90 dB Dynamic Range Integrated Stereo Headphone Amplifier Multibit - Converter Architecture for Improved S/N Ratio Greater than 90 dB 16-Bit Stereo Full-Duplex Codec Two Analog Line-Level Stereo Inputs for: LINE-IN and CD Mono MIC Input with Built-In Programmable Preamp High-Quality CD Input with Ground Sense Power Management Support 48-Terminal TQFP Package
AC'97 SoundMAX(R) Codec AD1887
ENHANCED FEATURES Full Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Software-Enabled VREFOUT Output for Microphones and External Power Amp Split Power Supplies (3.3 V Digital/5 V Analog) Mobile Low-Power Mixer Mode Extended 6-Bit Headphone Volume Control Digital Audio Mixer Mode
FUNCTIONAL BLOCK DIAGRAM
ID0 ID1
AD1887
MIC MIC PREAMP
CHIP SELECT
VREF
VREFOUT
CD
SELECTOR
LINE_IN
PGA
16-BIT - A/D CONVERTER
PGA
16-BIT - A/D CONVERTER
RESET SYNC
GA M
GA M
GA M
GA M
GA M M GA
SAMPLE RATE GENERATORS
AC LINK
BIT_CLK SDATA_OUT
16-BIT - A/D CONVERTER
SDATA_IN
SELECTOR
HP_OUT_L
HP
M
GA
M M M G = GAIN A = ATTENUATE M = MUTE
GA
16-BIT - A/D CONVERTER
HP_OUT_R
HP
M
GA
OSCILLATOR
XTL_OUT
XTL_IN
SoundMAX is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD1887-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25C DAC Test Conditions Digital Supply (VDD) 3.3 V Calibrated Analog Supply (VCC) 5.0 V -3 dB Attenuation Relative to Full Scale 48 kHz Sample Rate (fS) Input 0 dB Input Signal 1008 Hz 32 Output Load (HP_OUT) Analog Output Pass Band 20 Hz to 20 kHz 2.0 V VIH ADC Test Conditions VIL 0.8 V Calibrated VIH (CS0, CS1) 4.0 V 0 dB Gain 1.0 V VIL Input -3.0 dB Relative to Full Scale
ANALOG INPUT
Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, CD MIC with 20 dB Gain MIC with 0 dB Gain Input Impedance* Input Capacitance*
HEADPHONE OUT VOLUME
Min
Typ 1 2.83 0.1 0.283 1 2.83 20 5
Max
Unit V rms V p-p V rms V p-p V rms V p-p k pF
7.5
Parameter Step Size (+6 dB to -88.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental*
PROGRAMMABLE GAIN AMPLIFIER--ADC
Min
Typ 1.5 -94.5
Max
Unit dB dB dB
80
Parameter Step Size (0 dB to 22.5 dB) PGA Gain Range Span
ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS
Min
Typ 1.5 22.5
Max
Unit dB dB
Parameter Signal-to-Noise Ratio (SNR) CD to HP_OUT Other to HP_OUT Step Size (+12 dB to -34.5 dB): (All Steps Tested) MIC, LINE_IN, CD, DAC Input Gain/Attenuation Range: MIC, LINE_IN, CD, DAC
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Min
Typ 90 90 1.5 -46.5
Max
Unit dB dB dB dB
Parameter Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band
*Guaranteed but not tested.
Min 0 0.4 x fS 0.6 x fS -74
Typ
Max 0.4 x fS 0.09 0.6 x fS 12/fS 0.0
Unit Hz dB Hz Hz dB sec s
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AD1887
ANALOG-TO-DIGITAL CONVERTERS
Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 dB Input THD + N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Min
Typ 16 -84 87 85 -100 -90
Max
Unit Bits dB dB dB
84
-90 -85 10 0.5 5
dB dB % dB mV
Parameter Resolution Total Harmonic Distortion (THD) HP_OUT Dynamic Range (-60 dB Input THD + N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Audible Out-of-Band Energy (Measured from 0.6 x fS to 20 kHz)*
ANALOG OUTPUT
Min
Typ 16 -75 90 -100 10
Max
Unit Bits dB dB dB % dB dB dB
85
0.7 -80
-40
Parameter Full-Scale Output Voltage; HP_OUT Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance VREF VREF_OUT VREF_OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
STATIC DIGITAL SPECIFICATIONS
Min
Typ 1 2.83
Max
Unit V rms V p-p pF pF V V mA mV
800 32 15 100 2.45 5 5
2.05
2.25 2.25
Parameter High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), IOH = 2 mA Low-Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current
POWER SUPPLY
Min 0.65 x DVDD 0.9 x DVDD -10 -10
Typ
Max
Unit
V 0.35 x DVDD V V 0.1 x DVDD V +10 A +10 A
Parameter Power Supply Range--Analog (AVDD) Power Supply Range--Digital (DVDD) Power Dissipation--5 V/3.3 V Analog Supply Current--5 V (AVDD) Digital Supply Current--3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs)
*Guaranteed but not tested.
Min 4.75 3.15
Typ
Max 5.25 3.45
Unit V V mW mA mA dB
253 36 22 40
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AD1887-SPECIFICATIONS
CLOCK SPECIFICATIONS*
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN STATES
Min 40
Typ 24.576 50
Max 60
Unit MHz %
Parameter ADC DAC ADC + DAC ADC + DAC + Mixer (Analog CD On) Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Analog CD Only (AC-Link On) Analog CD Only (AC-Link Off) Standby Headphone Standby
*Guaranteed but not tested. Specifications subject to change without notice.
Set Bits PR0 PR1 PR1, PR0 LPMIX, PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 LPMIX, PR5, PR1, PR0 LPMIX, PR1, PR0, PR4, PR5 PR5, PR4, PR3, PR2, PR1, PR0 PR6
DVDD Typ 15.82 15.08 3.79 3.85 17.65 15.70 15.07 3.80 3.85 0.06 0.06 17.66
AVDD Typ 30.0 26.3 19.9 18.1 17.4 11.1 8.3 2.1 18.1 18.1 0 26.1
Unit mA mA mA mA mA mA mA mA mA mA mA mA
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
*Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
Min 162.8
Typ 1.0 1.3 19.5
Max
Unit s ns s s ns MHz ns ps ns ns kHz s ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns
162.8 12.288 81.4 32.56 32.56 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4 750 48.84 48.84
5 5 2 2 2 2 2 2 2 2 0 15
6 6 6 6 6 6 6 6 1.0 25 15 50 15
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AD1887
tRST_LOW
RESET
BIT_CLK
tRST2CLK
tRISECLK
SYNC
tFALLCLK
BIT_CLK
Figure 1. Cold Reset
tRISESYNC
SDATA_IN
tFALLSYNC
tSYNC_HIGH
SYNC BIT_CLK
tRST2CLK
SDATA_OUT
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
Figure 2. Warm Reset
Figure 5. Signal Rise and Fall Time
tCLK_LOW
SYNC
SLOT 1
SLOT 2
BIT_CLK
tCLK_HIGH tCLK_PERIOD
BIT_CLK
tSYNC_LOW
SYNC
SDATA_OUT
WRITE TO 0x26
DATA PR4
DON'T CARE
tS2_PDOWN
tSYNC_HIGH tSYNC_PERIOD
SDATA_IN NOTE: BIT_CLK NOT TO SCALE
Figure 3. Clock Timing
Figure 6. AC Link Low Power Mode Timing
tSETUP
RESET
BIT_CLK
SDATA_OUT
SYNC SDATA_OUT
SDATA_IN, BIT_CLK
tSETUP2RST
HI-Z
tHOLD
tOFF
Figure 4. Data Setup and Hold
Figure 7. ATE Test Mode
REV. 0
-5-
AD1887
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter Power Supplies Digital (DVDD) Analog (AVCC) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
Min -0.3 -0.3 -0.3 -0.3 0 -65
Max +3.6 +6.0 10.0 AVDD + 0.3 DVDD + 0.3 70 +150
Unit Model V V mA V V C C
Temperature Range
Package Description
Package Option
AD1887JST 0C to 70C
Thin-Quad Flatpack ST-48
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Rating TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package TQFP
JA JC CA
76.2C/W
17C/W
59.2C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1887 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
HP_OUT_R HP_OUT_L
AVDD3
AVDD2
ID0 AVSS3
AVSS2
ID1
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 NC 12
NC
36 35 34 33
PIN 1 IDENTIFIER
NC NC NC NC FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
AD1887
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24
CD_GND_REF
LINE_IN_L
CD_R MIC_IN
NC = NO CONNECT
-6-
LINE_IN_R
CD_L
NC
NC
NC
NC
NC
NC
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AD1887
PIN FUNCTION DESCRIPTIONS Digital I/O
Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET
Chip Selects
TQFP 2 3 5 6 8 10 11
I/O I O I O/I O I I
Description Crystal (or Clock) Input, 24.576 MHz Crystal Output AC-Link Serial Data Output, AD1887 Input Stream AC-Link Bit Clock 12288 MHz Serial Data Clock Daisy Chain Output Clock AC-Link Serial Data Input AD1887 Output Stream AC-Link Frame Sync AC-Link Reset AD1887 Master H/W Reset
Pin Name ID0 ID1
Analog I/O
TQFP 45 46
Type I I
Description Chip Select Input 0 (Active Low) Chip Select Input 1 (Active Low)
These signals connect the AD1887 component to analog sources and sinks, including microphones and speakers Pin Name CD_L CD_GND_REF CD_ R MIC LINE_IN_L LINE_IN_R HP_OUT_L HP_OUT_R
Filter/Reference
TQFP 18 19 20 21 23 24 39 41
I/O I I I I I I O O
Description CD Audio Left Channel CD Audio Analog Ground Reference for Differential CD Input CD Audio Right Channel Microphone Input Line in Left Channel Line in Right Channel Headphones Out Left Channel Headphones Out Right Channel
These signals are connected to resistors, capacitors, or specific voltages Pin Name VREF VREFOUT AFILT1 AFLIT2 FILT_R FILT_L TQFP 27 28 29 30 31 32 I/O O O O O O O Description Voltage Reference Filter Voltage Reference Output 5 mA Drive (Intended for Mic Bias) Antialiasing Filter Capacitor--ADC Right Channel Antialiasing Filter Capacitor--ADC Left Channel AC-Coupling Filter Capacitor--ADC Right Channel AC-Coupling Filter Capacitor--ADC Left Channel
Power and Ground Signals
Pin Name DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3
TQFP 1 4 7 9 25 26 38 40 43 44
Type I I I I I I I I I I
Description Digital VDD 33 V Digital GND Digital GND Digital VDD 33 V Analog VDD 50 V Analog GND Analog VDD 50 V Analog GND Analog VDD 50 V Analog GND
REV. 0
-7-
AD1887
No Connects
Pin Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
TQFP 12 13 14 15 16 17 22 33 34 35 36 37 42 47 48
Type
Description No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect
Indexed Control Registers
Reg Num
00h 04h 08h 00Eh 10h 12h 18h 1Ah 1Ch 20h 26h 28h 2Ah
Name Reset Headphones Volume Reserved Mic Volume Line-In Volume CD Volume PCM Out Vol Record Select Record Gain General-Purpose Power-Down Ctrl/Stat Ext'd Audio ID Ext'd Audio Stat/Ctrl
D15 X HPM X MCM LM CVM OM X IM X X ID1 X
D14 SE4 X X X X X X X X X X ID0 X SR14
D13 SE3 LHV5 X X X X X X X X PR5 X X SR13
D12 SE2 LHV4 X X LLV4 LCV4 LOV4 X X X PR4 X X SR12
D11 SE1 LHV3 X X LLV3 LCV3 LOV3 X LIM3 X PR3 X X SR11
D10 SE0 LHV2 X X LLV2 LCV2 LOV2 LS2 LIM2 X PR2 X X SR10
D9 ID9 LHV1 X X LLV1 LCV1 LOV1 LS1 LIM1 X PR1 X X SR9
D8 ID8 LHV0 X X LLV0 LCV0 LOV0 LS0 LIM0 X PR0 X X SR8
D7 ID7 X X X X X X X X
D6 ID6 X X M30 X X X X X
D5 ID5 RHV5 X X X X X X X X X X X SR5
D4 ID4 RHV4 X MCV4 RLV4 RCV4 ROV4 X X X X X X SR4
D3 ID3 RHV3 X MCV3 RLV3 RCV3 ROV3 X RIM3 X REF X X SR3
D2 ID2 RHV2 X
D1 ID1
D0 ID0
Default 0010h 8000h X
RHV1 RHV0 X X
MCV2 MCV1 MCV0 8008h RLV2 RCV2 ROV2 RS2 RIM2 X ANL X X SR2 RLV1 RLV0 8808h 8808h 8808h 0000h 8000h 0000h 000Xh 0005h 0000h BB80h
RCV1 RCV0 ROV1 ROV0 RS1 RIM1 X DAC X X SR1 RS0 RIM0 X ADC VRA VRA SR0
LPBK X X X X SR7 X X X SR6
2Ch/ PCM DAC Rate (SR1) SR15 (7Ah)* 32h/ PCM ADC Rate (SR0) SR15 (78h)* 74h Serial Configuration
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
BB80h
SLOT16 REGM2 REGM1 REGM0 X
X
X
X
X
X
X
X
X
X
X
X
7000h
76h
Misc Control Bits
DACZ
LPMIX X
DAM
DMS
DLSR
X
ALSR
MOD SRX10 SRX8 EN D7 D7 S7 S6 S5 REV5
X
X
DRSR
X
ARSR
0404h
7Ch 7Eh
Vendor ID1 Vendor ID2
F7 T7
F6 T6
F5 T5
F4 T4
F3 T3
F2 T2
F1 T1
F0 T0
S4 REV4
S3 REV3
S2 REV2
S1 REV1
S0 REV0
4144h 5362h
REV7 REV6
NOTES All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. *Indicates Aliased register for AD1819, AD1819A backward compatibility.
-8-
REV. 0
AD1887
Reset (Index 00h)
Reg Num 00h Name Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 D9 ID9 D8 D8 ID8 D7 D7 ID7 D6 D6 ID6 D5 D5 ID5 D4 D4 ID4 D3 D3 ID3 D2 D2 ID2 D1 D1 ID1 D0 D0 ID0 Default 0010h
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD1887 based on the following: Bit = 1 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 SE[4:0] Function Dedicated Mic PCM in Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1887* 0 0 0 0 1 0 0 0 0 0
*The AD1887 contains none of the optional features identified by these bits.
Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Headphones Volume Registers (Index 04h)
Reg Num 04h Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Headphones HPM Volume
X
LHV5
LHV4
LHV3
LHV2
LHV1 LHV0
X
X
RHV5 RHV4
RHV3
RHV2 RHV1 RHV0 8000h
RHV[5:0] LHV[5:0] HPM
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of -88.5 dB. Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of -88.5 dB. Headphones Volume Mute. When this bit is set to "1," the channel is muted. HPM 0 0 0 1 xHV5 . . . xHV0 00 0000 01 1111 11 1111 xx xxxx Function 6 dB Gain -40.5 dB Attenuation -88.5 dB Attenuation - dB Attenuation
REV. 0
-9-
AD1887
Mic Volume (Index 0Eh)
Reg Num 0Eh Name MIC Volume D15 MCM D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 M30 D5 D5 X D4 D4 MCV4 D3 D3 MCV3 D2 D2 MCV2 D1 D1 MCV1 D0 D0 MCV0 Default 8008h
MCV[4:0] M30 MCM
Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Mic Boost Gain: Amplifies the Mic input. 0 = 0 dB, 1 = 30 dB Mic Mute. When this bit is set to "1," the channel is muted.
Line In Volume (Index 10h)
Reg Num 10h N ame L in e In Volu me D 15 LM LM D 14 X D 13 X D 12 LLV4 D 11 LLV3 D 10 LLV2 D9 D9 LLV1 D8 D8 LLV0 D7 D7 X D6 D6 X D5 D5 X D4 D4 RLV4 D3 D3 RLV3 D2 D2 RLV2 D1 D1 RLV1 D0 D0 RLV0 D efau lt 8808h
RLV[4:0] LLV[4:0] LM
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Mute. When this bit is set to "1," the channel is muted.
CD Volume (Index 12h)
Reg Num 12h N ame CD CD Volu me D 15 D 14 D 13 X D 12 LCV4 D 11 LCV3 D 10 LCV2 D9 D9 LCV1 D8 D8 LCV0 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D efau lt
CVM X
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0] LCV[4:0] CVM
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to "1," the channel is muted.
-10-
REV. 0
AD1887
PCM Out Volume (Index 18h)
Reg Num 18h N ame PCM O u t Volu me D 15 OM OM D 14 X D 13 X D 12 D 11 D 10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D efau lt
LO V4 LO V3 LO V2 LO V1 LO V0 X
RO V4 RO V3 RO V2 RO V1 RO V0 8808h
ROV[4:0] LOV[4:0] OM
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to "1," the channel is muted.
Volume Table (Index 0Ch to 18h)
Mute 0 0 0 1
Record Select Control Register (Index 1Ah)
Reg Num 1Ah Name Record Select D15 X D14 X D13 X D12 X D11 X
x4 . . . x0 00000 01000 11111 xxxxx
Function +12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain
D10 LS2
D9 D9 LS1
D8 D8 LS0
D7 D7 X
D6 D6 X
D5 D5 X
D4 D4 X
D3 D3 X
D2 D2 RS2
D1 D1 RS1
D0 D0 RS0
Default 0000h
RS[2:0] LS[2:0]
Right Record Select Left Record Select
Used to select the record source independently for right and left. See table for legend. The default value is 0000h, which corresponds to Mic in. LS2 . . . LS0 0 1 4 5 6
Record Gain (Index 1Ch)
Reg Num 1Ch N ame R e c or d G a in D 15 IM IM D 14 X D 13 X D 12 X D 11 LIM 3 D 10 LIM 2 D9 D9 LIM 1 D8 D8 LIM 0 D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 RIM 3 D2 D2 RIM 2 D1 D1 RIM 1 D0 D0 RIM 0 D efau lt 8000h
Left Record Source MIC CD_L LINE_IN_L Stereo Mix (L) Mono Mix
RS2 . . . RS0 0 1 4 5 6
Right Record Source MIC CD_L LINE_IN_R Stereo Mix (R) Mono Mix
RIM[3:0] LIM[3:0] IM
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB. Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB. Input Mute 0 = Unmuted 1 = Muted or - dB Gain IM 0 0 1 xIM3 . . . xIM0 1111 0000 xxxxx Function 22.5 dB Gain 0 dB Gain - dB Gain
REV. 0
-11-
AD1887
General Purpose Register (Index 20h)
Reg Num 20h N ame G e n e r a l P u r pose D 15 X D 14 X D 13 X D 12 X D 11 X D 10 X D9 D9 X D8 D8 X D7 D7 LPB K D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 X D efau lt 0000h
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default value is 0000h, which is all off. LPBK Loopback Control. ADC/DAC digital loopback mode.
Subsection Ready Register (Index 26h)
Reg Num 26h Name Power-Down Cntrl/Stat D15 X D14 PR6 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 D9 PR1 D8 D8 PR0 D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 REF D2 D2 ANL D1 D1 DAC D0 D0 ADC Default NA NA
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1887 subsections. If the bit is a one, that subsection is "ready." Ready is defined as the subsection able to perform in its nominal state. ADC DAC ANL REF PR[5:0] ADC section ready to transmit data. DAC section ready to accept data. Analog gainuators, attenuators, and mixers ready. Voltage References, VREF and VREFOUT up to nominal level. AD1887 Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR0 - Powered-Down ADC PR1 - Powered-Down DAC PR2 - Powered-Down Analog Mixer PR3 - Powered-Down VREF and VREFOUT PR4 - Powered-Down AC-Link PR5 - Powered-Down Internal Clock PR6 - Powered-Down Headphone PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master's PR5 bit is clear, but the PR4 bit has no effect or disable PR5. Power-Down State ADC Power-Down DACs Power-Down ADC and DAC Power-Down Mixer Power-Down ADC + Mixer Power-Down DAC + Mixer Power-Down ADC + DAC + Mixer Power-Down Standby PR6 0 0 0 0 0 0 0 1 PR5 0 0 0 0 0 0 0 1 PR4 0 0 0 0 0 0 0 1 PR3 0 0 0 0 0 0 0 1 PR2 0 0 0 1 1 1 1 1 PR1 0 1 1 0 0 1 1 1 PR0 1 0 1 0 1 0 1 1
-12-
REV. 0
AD1887
Extended Audio ID Register (Index 28h)
Reg Num 28h N ame E x te n de d A u dio ID D 15 ID 1 D 14 ID 0 D 13 X D 12 X D 11 X D 10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 VRA D efau lt 0001h
Note: The Extended Audio ID is a read only register. VRA ID[1:0] Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio. ID1, ID0 is a 2-bit field which indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.
Extended Audio Status and Control Register (Index 2Ah)
Reg Num 2A h N ame E x t' d A u dio Sta t/ C tr l D 15 X D 14 X D 13 X D 12 X D 11 X D 10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 VRA D efau lt 0000h
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features. VRA Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio mode (sample rate control registers and SLOTREQ signaling).
PCM DAC Rate Register (Index 2Ch)
Reg Num N ame D 15 D 14 SR14 D 13 SR13 D 12 SR12 D 11 SR11 D 10 SR10 D9 D9 SR9 D8 D8 SR8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D efau lt
2 C h / (7 A h ) P C M D A C R a te SR 1 5
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 B B 80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg Num 3 2 h / (7 8 h ) N ame P C M A D C R a te D 15 D 14 D 13 D 12 D 11 D 10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D efau lt
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 B B 80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when read, otherwise the closest rate supported is returned.
REV. 0
-13-
AD1887
Serial Configuration (Index 74h)
Reg Num 74h Name Serial Configuration D15 D14 D13 REGM1 D12 REGM0 D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D5 D6 D5 X X D4 D3 D2 D1 D4 D3 D2 D1 X X X X D0 D0 X Default 7000h
SLOT 16 REGM2
Note: This register is not reset when the reset register (Register 00h) is written. DHWR REGM0 REGM1 REGM2 SLOT16 Disable Hardware Reset. Master Codec Register Mask. Slave 1 Codec Register Mask. Slave 2 Codec Register Mask. Enable 16-bit slots.
If your system uses only a single AD1887, you can ignore the register mask bits. SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.
Miscellaneous Control Bits (Index 76h)
Reg Num 76h Name D15 D14 LPMIX D13 D12 X D11 D10 D9 D8 D9 D8 ALSR D7 D7 MOD EN EN D6 D6 D5 D5 D4 D3 D2 D4 D3 D2 X D1 D0 D1 D0 Default
Misc DACZ Control Bits
DAM DMS
DLSR X
SRX10 SRX8 X D7 D7 D7 D7
DRSR X
ARSR 0404h
ARSR
ADC Right Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) DAC Right Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) Multiply SR1 rate by 8/7. Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set. Modem filter enable (left channel only). Change only when DACs are powered down. ADC Left Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) DAC Left Sample Generator Select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch) Digital Mono Select 0 = Mixer 1 = Left DAC + Right DAC Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output. Low-Power Mixer Zero-fill (vs. repeat) if DAC is starved for data.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
DMS
DAM LPMIX DACZ
-14-
REV. 0
AD1887
Sample Rate 0 (Index 78h)
Reg Num (32h)/78h Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default
Sample SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h Rate 0
Note: 32h is an alias for 78h. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48 kHz. SR0[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
Reg Num (2Ch)/7Ah Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default
Sample SR115 Rate 1
SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both sample rates are reset to 48 kHz. SR1[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Vendor ID Registers (Index 7Ch-7Eh)
Reg Num 7Ch N ame D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0 D9 D9 F6 F6 F5 F5 F4 F4 F3 F3 F2 F2 F1 F1 D8 D8 F0 F0 D7 D7 S7 S7 D6 D6 S6 S6 D5 D5 S5 S5 D4 D4 S4 S4 D3 D3 S3 S3 D2 D2 S2 S2 D1 D1 S1 S1 D0 D0 S0 S0 D efau lt 4144h
V e n d o r I D 1 F7 F7
S[7:0] F[7:0]
Reg Name Num 7Eh
This register is ASCII encoded to `A.' This register is ASCII encoded to `D.'
D15 D14 D13 D12 D11 D10 D9 D9 T7 T7 T6 T6 T5 T5 T4 T4 T3 T3 T2 T2 T1 T1 D8 D8 T0 T0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Vendor ID2
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5362h
T[7:0]
This register is ASCII encoded to `S.'
REV. 0
-15-
AD1887
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48)
C02497-.8-7/01(0)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
0.354 (9.00) BSC SQ
48 1 37 36
TOP VIEW
(PINS DOWN)
0.276 (7.00) BSC SQ
25
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0 MIN
12 13 24
0.019 (0.5) BSC 7 0
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
-16-
REV. 0
PRINTED IN U.S.A.

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